电子元器件制造技术

本发明专利技术提供一种电子元器件，能不使元件变大而降低LC并联谐振器的耦合度。层叠体(12)通过层叠多个绝缘体层(16)而构成。LC并联谐振器(LC1、LC2)是由在z轴方向上延伸的过孔导体、及设置于绝缘体层(16)上的导体层组成且呈环路状的LC并联谐振器，并构成带通滤波器。LC并联谐振器(LC1)的环路面(S1)和LC并联谐振器(LC2)的环路面(S2)与z轴方向平行且相互平行，并且在从环路面(S1)的法线方向俯视时，LC并联谐振器(LC1)的环路面(S1)和LC并联谐振器(LC2)的环路面(S2)的至少一部分相互重叠。环路面(S1)朝z轴方向的正方向一侧超出环路面(S2)。

Electronic components

The invention provides an electronic component, which can reduce the coupling degree of the LC parallel resonator without increasing the components. The laminate (12) is formed by stacking a plurality of insulator layers (16). The LC parallel resonator (LC1, LC2) is a LC parallel resonator composed of a through hole conductor extending in the direction of the Z axis and a conductor layer arranged on the insulator layer (16) and a band pass filter. LC (LC1) parallel resonator loop surface (S1) and LC (LC2) parallel resonator loop surface (S2) parallel to the Z axis direction and parallel to each other, and in the loop from the surface (S1) overlooking the normal direction, LC parallel resonator (LC1) loop surface (S1) and LC parallel resonator (LC2) the Ring Road (S2) at least a portion of the overlap. The loop surface (S1) extends beyond the loop surface (S2) in the positive direction of the Z axis.

【技术实现步骤摘要】
【国外来华专利技术】

【技术保护点】

【技术特征摘要】
【国外来华专利技术】...

【专利技术属性】
技术研发人员：增田博志，
申请(专利权)人：株式会社村田制作所，
类型：
国别省市：