A leakage current compensation device, which is characterized in that the power supply includes a first end, potential is lower than the first power of the second power supply terminal and an output terminal, one end connected to the first power terminal and the other end is connected to the output voltage or current regulations and has the conduction state and the off state first transistor at the end, with the first power supply terminal connection and set off state and the first transistor for the same type of second transistor, the second transistor is inserted from the other end of the output of the leakage current flowing through the second power of the path and the control end of the path connecting the third transistor, and the third transistor current mirror circuit and has the flowing through the third transistor power A fourth transistor that flows the corresponding current from the output to the driving power of the second power supply terminal.
【技术实现步骤摘要】
本专利技术涉及半导体装置的。
技术介绍
各种电路中包括具有ON状态及OFF状态的输出晶体管。在专利文献1及2中所述的是包括具有ON状态及OFF状态的输出晶体管的以往例子的稳压电源电路。图5为以往例子的稳压电路电路的电路图。在图5中，1为运算放大器，2为输出电压VA的基准电压源，3为是PMOS晶体管输出晶体管，4为输出端，5为输入电源电压的电源端，6为NMOS晶体管，7为控制端，8、9及16为电阻元件。基准电压源2与运算放大器1的反相输入端连接，其输出端与PMOS晶体管3的栅极连接。PMOS晶体管3的源极与电源端5连接，漏极与输出端4和电阻元件8及16连接。PMOS晶体管3的漏极通过电阻元件8与9的串连电路接地。电阻元件8与电阻元件9的连接点与运算放大器1的同相输入端连接。用电阻元件8及9将PMOS晶体管3的漏极电压进行分压后的电压加在运算放大器1的反相输入端上。控制端7与NMOS晶体管6的栅极及运算放大器1的控制端连接。NMOS晶体管6的源极接地，漏极通过电阻元件16与PMOS晶体管3的漏极连接。设电阻元件8、9及16的电阻值分别为R1、R2及R3。在上述构成...
【技术保护点】
【技术特征摘要】
【专利技术属性】
技术研发人员：木原秀之，
申请(专利权)人：松下电器产业株式会社，
类型：发明
国别省市：
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