异质结遂穿场效应晶体管及其制备方法技术

本申请实施例提供一种异质结遂穿场效应晶体管及其制备方法，包括：第一绝缘层覆盖在衬底的上表面，第一异质结材料层覆盖在第一绝缘层的上表面上用于设置源极的一端，源极设置在第一异质结材料层的一端，第一异质结材料层另一端周围设置有第二绝缘层，隔离层设置在异质结层上，隔离层覆盖在源极的内侧；第二异质结材料层覆盖在第一异质结材料层的另一端、第二绝缘层以及第二绝缘层上，与第一异质结材料层形成异质结，漏极设置在第二异质结层上与源极相对的另一端；栅介质层覆盖在第二异质结材料层上位于源极和漏极之间的位置，栅极设置在栅介质层上。通过设置第二绝缘层进行隔离，显著减小边缘态导致的泄露电流，并利用二维材料形成异质结，避免了因晶格不匹配导致的界面缺陷。

Heterojunction tunneling field effect transistor and its preparation method

The embodiment of this application provides a heterojunction tunneling field effect transistor and a preparation method thereof, including: a first insulating layer covers the upper surface of the substrate, a first heterojunction material layer covers one end of the upper surface of the first insulating layer for setting a source, a source pole is located at one end of the first heterojunction material layer, and a second insulating layer is arranged around the other end of the first heterojunction material layer. The isolation layer is set on the heterojunction layer, and the isolation layer covers the inner side of the source; the second heterojunction material layer covers the other end of the first heterojunction material layer, the second insulating layer and the second insulating layer, forming a heterojunction with the first heterojunction material layer, and the drain is set on the other end opposite to the source on the second heterojunction layer; the gate dielectric layer covers the second heterojunction material layer. At the position between the source and drain, the gate is arranged on the gate dielectric layer. By setting a second insulating layer for isolation, the leakage current caused by the edge state is significantly reduced, and the two-dimensional material is used to form a heterojunction, thus avoiding the interface defects caused by lattice mismatch.

【技术实现步骤摘要】
【国外来华专利技术】PCT国内申请，说明书已公开。

【技术保护点】
PCT国内申请，权利要求书已公开。

【技术特征摘要】
【国外来华专利技术】PCT国内申请，...

【专利技术属性】
技术研发人员：李伟，徐挽杰，徐慧龙，张臣雄，
申请(专利权)人：华为技术有限公司，
类型：发明
国别省市：广东,44