The invention discloses a FPGA circuit. In one embodiment, the FPGA circuit includes a configuration memory for storing FPGA configuration files, configuration files including the configuration data and the ECC code and CRC code; ECC hardware decoder, error correction and error detection of configuration data using ECC code; hardware CRC decoder, error correction of configuration data using CRC code; SEU the controller used for read configuration files, and use hardware ECC decoder and CRC decoder hardware check and correction of the read back configuration file, an error state, information recording configuration file; according to the detection of CRC, ECC hardware decoder, corresponding control, and send a wrong signal to the application, request to FPGA configuration file. By using this circuit, the ability of FPGA to support single event upset is greatly enhanced, so that FPGA can be applied to aerospace, aviation or other areas that are sensitive to equipment errors, so it has broad and significant significance.
【技术实现步骤摘要】
【国外来华专利技术】PCT国内申请,说明书已公开。
【技术保护点】
PCT国内申请,权利要求书已公开。
【技术特征摘要】
【国外来华专利技术】PCT国内申请,...
【专利技术属性】
技术研发人员:何轲,
申请(专利权)人:京微雅格北京科技有限公司,
类型:发明
国别省市:北京,11
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