The utility model discloses a novel driving circuit for AC charging pile magnetic holding relay, which comprises a logic chip U 2 and a two-input XOR gate U3. The foot 2 of the logic chip U2 is connected to resistance R45 after connecting resistance R11 in series, resistance R45 is connected to foot 1 of transistor Q2, foot 3 of logic chip U2 is connected to resistance R13 after connecting resistance R13 in series with foot 4 of two-input XOR gate U3, and foot 5 of logic chip U2 is connected to resistance R16 in series. The resistance R44 is connected to the foot 1 of transistor Q 1, the foot 9 of logic chip U2 is connected to the resistance R18, and then to the reset relay signal terminal K1_CLOSED_CTR. The foot 10 of logic chip U2 is connected to the resistance R17, and then to the open relay signal terminal K_OPEN_CTR. The driving circuit of the new AC charging pile magnetic retaining relay simplifies the software control flow and interlocks the hardware. All the functions of the traditional magnetic retaining relay can be realized by switching on the relay signal terminal K_OPEN_CTR and the reset relay signal terminal K1_CLOSED_CTR.
【技术实现步骤摘要】
一种新型交流充电桩磁保持继电器驱动电路
本技术涉及继电器
,具体为一种新型交流充电桩磁保持继电器驱动电路。
技术介绍
传统磁保持继电器相比普通继电器,只需脉冲驱动,带有磁保持功能,可以减少线圈损耗,降低继电器发热,适应于大电流,发热要求低的应用场合;它有二个线圈驱动,一边为开通线圈,一边为复位线圈,即开通线圈驱动,可以接通触点,开通继电器;开通复位驱动,为关闭线圈驱动,可以断开触点,关闭继电器。传统的驱动方式,通过四个控制信号,直接控制继电器K1开、K1关以及K2开、K2关,其缺点是:控制信号占用IO口多,要求软件开关信号实现互补,逻辑复杂。
技术实现思路
本技术的目的在于提供一种新型交流充电桩磁保持继电器驱动电路,简化软件控制流程,并使硬件实现互锁,只需开关开继电器信号端子K_OPEN_CTR与复位继电器信号端子K1_CLOSED_CTR即可实现传统磁保持继电器的所有功能,解决了现有技术中的问题。为实现上述目的,本技术提供如下技术方案:一种新型交流充电桩磁保持继电器驱动电路,包括逻辑芯片U2和二输入异或门U3,所述逻辑芯片U2的脚2串接电阻R11后连接于电阻R45 ...
【技术保护点】
1.一种新型交流充电桩磁保持继电器驱动电路,包括逻辑芯片U2和二输入异或门U3,其特征在于:所述逻辑芯片U2的脚2串接电阻R11后连接于电阻R45,电阻R45连接于三极管Q2的脚1,逻辑芯片U2的脚3串接电阻R13后连接于二输入异或门U3的脚4,逻辑芯片U2的脚5串接电阻R16后连接于电阻R44,电阻R44连接于三极管Q1的脚1,逻辑芯片U2的脚9串接电阻R18后连接于复位继电器信号端子K1_CLOSED_CTR,逻辑芯片U2的脚10串接电阻R17后连接于开继电器信号端子K_OPEN_CTR,逻辑芯片U2的脚13串接电阻R15后连接于输出信号端子K_SIG,逻辑芯片U2的脚 ...
【技术特征摘要】
1.一种新型交流充电桩磁保持继电器驱动电路,包括逻辑芯片U2和二输入异或门U3,其特征在于:所述逻辑芯片U2的脚2串接电阻R11后连接于电阻R45,电阻R45连接于三极管Q2的脚1,逻辑芯片U2的脚3串接电阻R13后连接于二输入异或门U3的脚4,逻辑芯片U2的脚5串接电阻R16后连接于电阻R44,电阻R44连接于三极管Q1的脚1,逻辑芯片U2的脚9串接电阻R18后连接于复位继电器信号端子K1_CLOSED_CTR,逻辑芯片U2的脚10串接电阻R17后连接于开继电器信号端子K_OPEN_CTR,逻辑芯片U2的脚13串接电阻R15后连接于输出信号端子K_SIG,逻辑芯片U2的脚14串接电阻R14后连接于电阻R54,电阻R54连接于三极管Q3的脚1,逻辑芯片U2的脚12串接电阻R12后连接于电阻R55,电阻R55连接于三极管Q4的脚1;所述二输入异或门U3的脚1串接电阻R22后连接于电阻R17的电路接口,二输入异或门U3的脚2串接电...
【专利技术属性】
技术研发人员:梁立贤,尹进均,
申请(专利权)人:广东爱普拉新能源技术股份有限公司,
类型:新型
国别省市:广东,44
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