【技术实现步骤摘要】
⊕
x
28
, t
85 = x3⊕
x
26
;所述线性层M0实现电路第二模块的输入信号为:x6, x8, x
10
, x
13
, x
21
, x
22
, x
27
, t
32
, t
34
, t
35
, t
37
, t
39
, t
54
, t
59
;输出信号为:t
36
, t
38
, t
40
, t
42
, t
55
, t
60
, t
64
, t
73
, t
81
,具体包含9个异或门电路,分别为:t
36 = x
10
⊕
t
35
, t
38 = x
21
⊕
t
37
, t
40 = t
37
⊕
t
39
, t
42 = x6⊕
t
39
, t
55 = x8⊕
t
54
, t
60 = t
34
⊕
t
59
, t
64 = x
22 >⊕
t
59
, t
73 = x
27
⊕
t
54
, t
81 = x
13
⊕
t
32
;所述线性层M0实现电路第三模块的输入信号为:x7, x
13
, x
15
, x
22
, x
25
, x
29
, x
31
, t
32
, t
38
, t
40
, t
42
, t
52
, t
55
, t
60
, t
64
, t
72
, t
73
, t
81
,输出信号为:y
23
, t
43
, t
47
, y1, t
57
, y7, t
65
, t
74
, t
83
, y
30
,具体包含10个异或门电路,分别为:t
41 = x
13
⊕
t
40
= y
23
, t
43 = x
15
⊕
t
42
, t
47 = x7⊕
t
42
, t
56 = t
52
⊕
t
55 = y1, t
57 = x
25
⊕
t
55
, t
61 = x
29
⊕
t
60 = y7, t
65 = x
31
⊕
t
64
, t
74 = t
72
⊕
t
73
, t
83 = x
22
⊕
t
81
, t
97 = t
32
⊕
t
38 = y
30
;所述线性层M0实现电路第四模块的输入信号为:x0, x2, x
16
, x
18
, x
20
, x
24
, x
29
, t
35
, t
43
, t
47
, t
55
, t
57
, t
61
, t
65
, t
72
, t
74
, t
76
, t
83
,输出信号为:t
44
, t
45
, y
24
, t
50
, t
58
, t
62
, y8, t
67
, t
68
, t
75
, y5, t
78
, y
22
,具体包含13个异或门电路,分别为:t
44 = t
35
⊕
t
43
, t
45 = x0⊕
t
43
, t
48 = x
24
⊕
t
47 = y
24
, t
50 = x2⊕
t
43
, t
58 = x
18
⊕
t
57
, t
62 = t
47
⊕
t
61
, t
66 = t
55
⊕
t
65 = y8, t
67 = x
16
⊕
t
65
, t
68 = t
47
⊕
t
65
, t
75 = x
20
⊕
t
74
, t
77 = t
74
⊕
t
76 = y5, t
78 = t
47
⊕
t
72
, t
84 = x
29
⊕
t
83 =y
22
;所述线性层M0实现电路第五模块的输入信号为:x9, x
10
, x
17
, x
19
, x
25
, x
26
, t
33
, t
34
, t
36
, t
41
, t
44
, t
45
, t
48
, t
50
, t
58
, t
62
, t
本文档来自技高网...
【技术保护点】
【技术特征摘要】
t
70 = x
17
⊕
t
44
, t
79 = x
10
⊕
t
78
, t
82 = t
75
⊕
t
81 = y
13
, t
86 = t
78
⊕
t
85
, t
91 = x
19
⊕
t
50
, t
98 = t
34
⊕
t
75
, t
103 = t
36
⊕
t
67
, t
105 = x9⊕
t
45
, t
108 = t
33
⊕
t
58
, t
110 = t
45
⊕
t
68 =y0, t
127 = t
41
⊕
t
68
= y
31
;所述线性层M0实现电路第六模块的输入信号为:x1, x
10
, x
18
, t
33
, t
44
, t
49
, t
51
, t
52
, t
56
, t
58
, t
66
, t
69
, t
70
, t
77
, t
79
, t
86
, t
91
, t
98
, t
103
, t
105
, t
108
, t
110
;输出信号为:t
53
, t
71
, t
80
, t
87
, t
88
, t
92
, t
109
, y
14
, y
18
, y
10
, t
118
, y
25
,具体包含12个异或门电路,分别为:t
53 = t
49
⊕
t
52
, t
71 = t
66
⊕
t
70
, t
80 = t
33
⊕
t
79
, t
87 = x
18
⊕
t
86
, t
88 = x1⊕
t
51
, t
92 = x
10
⊕
t
91
, t
109 = t
44
⊕
t
108
, t
115 = t
77
⊕
t
98 [y
14
], t
116 = t
58
⊕
t
105 = y
18
, t
117 = t
56
⊕
t
103 = y
10
, t
118 = t
51
⊕
t
69
, t
122 = t
69
⊕
t
110 = y
25
;所述线性层M0实现电路第七模块的输入信号为:x3, x
21
, t
46
, t
48
, t
53
, t
61
, t
63
, t
67
, t
68
, t
71
, t
75
, t
80
, t
86
, t
87
, t
88
, t
92
, t
109
, t
118
, t
115
;输出信号为:t
89
, t
93
, y
26
, t
99
, y
20
, y
12
, y
16
, y
11
, y2, y
15
, y6,具体包含11个异或门电路,分别为:t
89 = t
86
⊕
t
88
, t
93 = x3⊕
t
92
, t
96 = t
46
⊕
t
53 = y
26
, t
99 = x
21
⊕
t
80
, t
101 = t
75
⊕
t
80 = y
20
, t
107 = t
68
⊕
t
87 = y
12
, t
111 = t
67
⊕
t
71 = y
16
, t
120 = t
71
⊕
t
109 = y
11
, t
124 = t
48
⊕
t
118
= y2, t
125 = t
61
⊕
t
71 = y
15
, t
126 = t
63
⊕
t
115 =y6;所述线性层M0实现电路第八模块的输入信号为:x
27
, x
28
, t
74
, t
80
, t
89
, t
93
, t
105
, t
107
, t
111
;输出信号为:t
90
, t
94
, y
28
, t
113
, y9,具体包含5个异或门电路,分别为:t
90
=x
27
⊕
t
89
, t
94 = t
74
⊕
t
93
, t
95 = x
28
⊕
t
93
=y
28
, t
113 = t
80
⊕
t
107
, t
121
= t
105
⊕
t
111
= y9;所述线性层M0实现电路第九模块的输入信号为:t
32
, t
87
, t
90
, t
94
, t
95
, t
99
, t
109
, t
113
;输出信号为:t
100
, y
19
, y
27
, y
21
, y3,具体包含5个异或门电路,分别为:t
100 = t
32
⊕
t
94
, t
102 = t
90
⊕
t
94 = y
19
, t
106 = t
87
⊕
t
90 = y
27
, t
112 = t
95
⊕
t
99 = y
21
, t
119 = t
109
⊕
t
113 = y3;所述线性层M0实现电路第十模块的输入信号为x
29
, t
100
, t
113
,输出信号为t
104
, y4,具体包含2个异或门电路,分别为t
104 = x
29
⊕
t
100
, t
114 = t
100
⊕
t
113 = y4;所述线性层M0实现电路第十一模块的输入信号为t
101
, t
104
;输出信号为y
29
,异或门电路为t
123 = t
101
⊕
t
104 = y
29
。2.根据权利要求1所述的优化的CLEFIA算法线性层实现电路,其特征在于,线性层M1实现电路包含10个模块;
所述线性层M1实现电路第一模块的输入信号为:x0, x1, x2, x3, x4, x5, x6, x7, x8, x
10
, x
11
, x
12
, x
13
, x
14
, x
15
, x
16
, x
18
, x
20
, x
22
, x
24
, x
25, x
26
, x
28, x
29
, x
30
, x
31
;输出信号为:t
32
, t
33
, t
34
, t
35
, t
37
, t
40
, t
41
, t
44
, t
45
, t
46
, t
47
, t
48
, t
49
, t
50
, t
52
, t
70
, t
101
,具体包含17个异或门电路,分别为:t
32 = x
29
⊕
x
13
, t
33 = x6⊕
x
22
, t
34 = x
15
⊕
x
31
, t
35 = x
14
⊕
x
30
, t
37 = x5⊕
x
13
, t
40 = x
16
⊕
x
24
, t
41 = x0⊕
x8, t
44 = x
12
⊕
x
28
, t
45 = x4⊕
x
20
, t
46 = x
10
⊕
x
20
, t
47 = x2⊕
x
10
, t
48 = x
10
⊕
x
25
, t
49 = x
26
⊕
x
28
, t
50 = x
18
⊕
x
26
, t
52
= x1⊕
x
18
, t
70 = x3⊕
x
11
, t
101
= x7⊕
x
22
;所述线性层M1实现电路第二模块的输入信号为:x1, x9, x
11
, x
17
, x
21
, x
25
, x
30
, x
31
, t
32
, t
33
, t
34
, t
35
, t
37
, t
40
, t
44
, t
45
, t
46
, t
50
, t
70
;输出信号为:t
36
, t
38
, t
42
, t
54
, t
55
, t
60
, t
61
, t
62
, t
71
, t
73
, t
76
, t
81
, t
91
,具体包含13个异或门电路,分别为:t
36 = x
31
⊕
t
32
, t
38 = x
21
⊕
t
32
, t
42 = t
37
⊕
t
34
, t
54 = x
25
⊕
t
33
, t
55 = x1⊕
t
40
, t
60 = t
33
⊕
t
34
, t
61 = x9⊕
t
46
, t
62 = x9⊕
t
33
, t
71 = x
17
⊕
t
70
, t
73 = t
35
⊕
t
70
, t
76 = t
44
⊕
t
45
, t
81 = x
11
⊕
t
50
, t
91 = x
30
⊕
t
44
;所述线性层M1实现电路第三模块的输入信号为:x5, x7, x
16
, x
19
, x
23
, x...
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