The embodiment of the invention discloses a field effect transistor structure and its fabrication method. The structure of the field effect transistor includes a bottom gate electrode, a bottom gate dielectric layer and a nanostrip channel layer, which is composed of a plurality of parallel spaced double-layer graphene nanostrips. The nanostrip channel layer covers the upper surface of the bottom gate dielectric layer, and the nanostrip channel layer is said to be connected with the bottom gate dielectric layer. Upper surface contact of bottom gate dielectric layer; source and drain; top gate dielectric layer; top gate electrode. The structure and fabrication method of the field effect transistor provided in the embodiment of the invention can effectively reduce the influence of the charge center of the gate dielectric without sacrificing the open current of the device, so that the device can be turned off better and the switch ratio of the device can be increased.
【技术实现步骤摘要】
【国外来华专利技术】PCT国内申请,说明书已公开。
【技术保护点】
PCT国内申请,权利要求书已公开。
【技术特征摘要】
【国外来华专利技术】PCT国内申请,...
【专利技术属性】
技术研发人员:秦旭东,徐慧龙,张臣雄,
申请(专利权)人:华为技术有限公司,
类型:发明
国别省市:广东,44
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